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? semiconductor components industries, llc, 2009 december, 2009 ? rev. 0 1 publication order number: NCL30000/d NCL30000 power factor corrected dimmable led driver the NCL30000 is a switch mode power supply controller intended for low to medium power single stage power factor (pf) corrected led drivers. the device is designed to operate in critical conduction mode (crm) and is suitable for flyback as well as buck topologies. constant on time crm operation is particularly suited for isolated flyback led applications as the control scheme is straightforward and very high efficiency can be achieved even at low power levels. these are important in led lighting to comply with regulatory requirements and meet overall system luminous efficacy requirements. in crm, the switching frequency will vary with line and load and switching losses are low as recovery losses in the output rectifier are negligible since the current goes to zero prior to reactivating the main mosfet switch. the device features a programmable on time limiter, zero current detect sense block, gate driver, trans ? conductance error amplifier as well as all pwm control circuitry and protection functions required to implement a crm switch mode power supply. moreover, for high efficiency, the device features low startup current enabling fast, low loss charging of the v cc capacitor. the current sense protection threshold has been set at 500 mv to minimize power dissipation in the external sense resistor. to support the environmental operation range of solid state lighting, the device is specified across a wide junction temperature range of ? 40 c to 125 c. features ? very low 24 a typical startup current ? constant on time pwm control ? cycle ? by ? cycle current protection ? low current sense threshold of 500 mv ? low 2 ma typical operating current ? source 500 ma / sink 800 ma totem pole gate driver ? reference design for triac and trailing edge line dimmers ? wide operating temperature range ? no input voltage sensing requirement ? enable function and overvoltage protection ? these devices are pb ? free, halogen free/bfr free and are rohs compliant typical applications ? led driver power supplies ? led based down lights ? commercial and residential led fixtures ? triac dimmable led based par lamps ? power factor corrected constant voltage supplies http://onsemi.com soic ? 8 d suffix case 751 marking diagram pin connection 1 8 a = assembly location l = wafer lot y = year w = work week = pb ? free package l0000 alyw 1 8 mfp comp ct cs v cc drv gnd zcd (top view) device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. NCL30000dr2g soic ? 8 (pb ? free) 2500 / tape & reel
NCL30000 http://onsemi.com 2 + figure 1. block diagram e/a demag uvp fault leb 195 ns* off timer reset pwm r q s (enable ea) drv q all sr latches are reset dominant zcd clamp ovp v cc drv gnd v dd v cc mfp zcd c t cs comp + + ? v ovp ? + v uvp r mfp v ref + g m ? + v control r q s q r q s q r q s q v zcd(trig) ? + + v zcd(arm) + + ? + ? + v dd add ct offset 275 a* v eah clamp ? + 180 s* v cc management v dd power good v dd ocp v ilim * typical values shown
NCL30000 http://onsemi.com 3 table 1. pin function description pin name function 1 mfp the multi ? function pin is connected to the internal error amplifier. by pulling this pin below the v uvp threshold, the controller is disabled. in addition, this pin also has an over voltage comparator which will disable the controller in the event of a fault. 2 comp the comp pin is the output of the internal error amplifier. a compensation network is connected between this pin and ground to set the loop bandwidth. normally this bandwidth is set at a low frequency (typically 10 hz ? 20 hz) to achieve high power factor and low total harmonic distortion (thd). 3 c t the c t pin sources a regulated current to charge an external timing capacitor. the pwm circuit controls the power switch on time by comparing the c t voltage to an internal voltage derived from v control . the c t pin discharges the external timing capacitor at the end of the on time cycle. 4 cs the cs input is used to sense the instantaneous switch current in the external mosfet. this signal is filtered by an internal leading edge blanking circuit. 5 zcd the voltage of an auxiliary zero current detection winding is sensed at this pin. when the zcd control block circuit detects that the winding has been demagnetized, a control signal is sent to the gate drive block to turn on the external mosfet. 6 gnd this is the analog ground for the device. all bypassing components should be connected to the gnd pin with a short trace length. 7 drv the high current capability of the totem pole gate drive (+0.5/ ? 0.8 a) makes it suitable to effectively drive high gate charge power mosfets. the driver stage provides both passive and active pull down circuits that force the output to a voltage less than the turn ? on threshold voltage of the power mosfet when v cc(on) is not reached. 8 v cc this pin is the positive supply of the controller. the circuit starts to operate when v cc exceeds v cc(on) , nominally 12 v and turns off when v cc goes below v cc(off) , typically 9.5 v. after startup, the operating range is 10.2 v up to 20 v.
NCL30000 http://onsemi.com 4 q1 emi filter 1 2 3 4 8 7 6 5 c in r cs ? ? ? ? ?? ?? ? ncs1002 in1 ? in2 ? in2+ out1 out2 vcc NCL30000 + ? + ? c c c v figure 2. simplified flyback application with secondary side constant current control overview figure 2 illustrates how the NCL30000 is configured to implement an isolated power factor corrected flyback switch mode power supply. on the secondary side is the ncs1002, a constant voltage, constant current controller which senses the average led current and the output voltage and provides a feedback control signal to the primary side through an opto ? coupler interface. one of the key benefits of active power factor correction is that it makes the load appear like a linear resistance similar to an incandescent bulb. high power factor requires generally sinusoidal line current and minimal phase displacement between the line current and voltage. the NCL30000 operates in a fixed on ? time variable frequency mode where the power switch is on for the same length of time over a half cycle of input power. the current in the primary of the transformer starts at zero each switching cycle and is directly proportional to the applied voltage times the on ? time. therefore with a fixed on ? time, the current will follow the applied voltage generating a current of the same shape. just as in a traditional boost pfc circuit, the control bandwidth is low so that the on ? time is constant throughout a single line cycle. the feedback signal from the secondary side is used to modify the average on ? time so the current through the leds is properly regulated regardless of forward voltage variation of the led string.
NCL30000 http://onsemi.com 5 table 2. maximum ratings rating symbol value unit mfp voltage v mfp ? 0.3 to 10 v mfp current i mfp 10 ma comp voltage v control ? 0.3 to 6.5 v comp current i control ? 2 to 10 ma ct voltage v ct ? 0.3 to 6 v ct current i ct 10 ma cs voltage v cs ? 0.3 to 6 v cs current i cs 10 ma zcd voltage v zcd ? 0.3 to 10 v zcd current i zcd 10 ma drv voltage v drv ? 0.3 to v cc v drv sink current i drv(sink) 800 ma drv source current i drv(source) 500 ma supply voltage v cc ? 0.3 to 20 v supply current i cc 20 ma power dissipation (t a = 70 c, 2.0 oz cu, 55 mm 2 printed circuit copper clad) p d 450 mw thermal resistance junction ? to ? ambient (2.0 oz cu, 55 mm 2 printed circuit copper clad) junction ? to ? air, low conductivity pcb (note 3) junction ? to ? air, high conductivity pcb (note 4) r ja r ja r ja 178 168 127 c/w operating junction temperature range t j ? 40 to 125 c maximum junction temperature t j(max) 150 c storage temperature range t stg ? 65 to 150 c lead temperature (soldering, 10 s) t l 300 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: pins 1? 8: human body model 2000 v per jedec standard jesd22 ? a114e. pins 1? 8: machine model method 200 v per jedec standard jesd22 ? a115 ? a. 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. 3. as mounted on a 40x40x1.5 mm fr4 substrate with a single layer of 80 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 low conductivity test pcb. test conditions were under natural convection or zero air flow. 4. as mounted on a 40 x 40 x 1.5 mm fr4 substrate with a single layer of 650 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 high conductivity test pcb. test conditions were under natural convection or zero air flow. table 3. electrical characteristics v mfp = 2.4 v, v control = 4 v, ct = 1 nf, v cs = 0 v, v zcd = 0 v, c drv = 1 nf, v cc = 12 v, unless otherwise specified (for typical values, t j = 25 c. for min/max values, t j = ? 40 c to 125 c, unless otherwise specified) characteristic test conditions symbol min typ max unit startup and supply circuits startup voltage threshold v cc increasing v cc(on) 11 12 12.5 v minimum operating voltage v cc decreasing v cc(off) 8.8 9.5 10.2 v supply voltage hysteresis h uvlo 2.2 2.5 2.8 v startup current consumption 0 v < v cc < v cc(on) ? 200 mv i cc(startup) ? 24 35 a no load switching current consumption c drv = open, 70 khz switching, v cs = 2 v i cc1 ? 1.4 1.7 ma switching current consumption 70 khz switching, v cs = 2 v i cc2 ? 2.1 2.6 ma fault condition current consumption no switching, v mfp = 0 v i cc(fault) ? 0.75 0.95 ma
NCL30000 http://onsemi.com 6 table 3. electrical characteristics (continued) v mfp = 2.4 v, v control = 4 v, ct = 1 nf, v cs = 0 v, v zcd = 0 v, c drv = 1 nf, v cc = 12 v, unless otherwise specified (for typical values, t j = 25 c. for min/max values, t j = ? 40 c to 125 c, unless otherwise specified) characteristic unit max typ min symbol test conditions overvoltage and undervoltage protection overvoltage detect threshold v mfp = increasing v ovp /v ref 105 106 108 % overvoltage hysteresis v ovp(hys) 20 60 100 mv overvoltage detect threshold propagation delay v mfp = 2 v to 3 v ramp, dv/dt = 1 v/ s v mfp = v ovp to v drv = 10% t ovp ? 500 800 ns undervoltage detect threshold v mfp = decreasing v uvp 0.25 0.31 0.4 v undervoltage detect threshold propagation delay v mfp = 1 v to 0 v ramp, dv/dt = 10 v/ s v mfp = v uvp to v drv = 10% t uvp 100 200 300 ns error amplifier voltage reference t j = 25 c t j = ? 40 c to 125 c v ref 2.475 2.460 2.500 2.500 2.525 2.540 v voltage reference line regulation v cc(on) + 200 mv < v cc < 20 v v ref(line) ? 10 ? 10 mv error amplifier current capability v mfp = 2.6 v v mfp = 1.08*v ref v mfp = 0.5 v i ea(sink) i ea(sink)ovp i ea(source) 6 10 ? 11 0 10 20 ? 210 20 30 ? 250 a transconductance v mfp = 2.4 v to 2.6 v t j = 25 c t j = ? 40 c to 125 c gm 90 70 110 110 120 135 s feedback pin internal pull ? down resistor v mfp = v uvp to v ref r mfp 2 4.6 10 m feedback bias current v mfp = 2.5 v i mfp 0.25 0.54 1.25 a control bias current v mfp = 0 v i control ? 1 ? 1 a maximum control voltage i control(pullup) = 10 a, v mfp = v ref v eah 5 5.5 6 v minimum control voltage to generate drive pulses v control = decreasing until v drv is low, v ct = 0 v ct (offset) 0.37 0.65 0.88 v control voltage range v eah ? ct (offset) v ea(diff) 4.5 4.9 5.3 v
NCL30000 http://onsemi.com 7 table 3. electrical characteristics (continued) v mfp = 2.4 v, v control = 4 v, ct = 1 nf, v cs = 0 v, v zcd = 0 v, c drv = 1 nf, v cc = 12 v, unless otherwise specified (for typical values, t j = 25 c. for min/max values, t j = ? 40 c to 125 c, unless otherwise specified) characteristic unit max typ min symbol test conditions ramp control ct peak voltage v comp = open v ct(max) 4.775 4.93 5.025 v on time capacitor charge current v comp = open v ct = 0 v to v ct(max) i charge 235 275 297 a ct capacitor discharge duration v comp = open v ct = v ct(max) ? 100 mv to 500 mv t ct(discharge) ? 50 150 ns pwm propagation delay dv/dt = 30 v/ s v ct = v control ? ct (offset) to v drv = 10% t pwm ? 130 220 ns zero current detection zcd arming threshold v zcd = increasing v zcd(arm) 1.25 1.4 1.55 v zcd triggering threshold v zcd = decreasing v zcd(trig) 0.6 0.7 0.83 v zcd hysteresis v zcd(hys) 500 700 900 mv zcd bias current v zcd = 5 v i zcd ? 2 ? + 2 a positive clamp voltage i zcd = 3 ma v cl(pos) 9.8 10 12 v negative clamp voltage i zcd = ? 2 ma v cl(neg) ? 0.9 ? 0.7 ? 0.5 v zcd propagation delay v zcd = 2 v to 0 v ramp, dv/dt = 20 v/ s v zcd = v zcd(trig) to v drv = 90% t zcd ? 100 170 ns minimum zcd pulse width t sync ? 70 ? ns maximum off time in absence of zcd transition falling v drv = 10% to rising v drv = 90% t start 75 165 300 s drive drive resistance i source = 100 ma i sink = 100 ma r oh r ol ? ? 12 6 20 13 rise time 10% to 90% t rise ? 35 80 ns fall time 90% to 10% t fall ? 25 70 ns drive low voltage v cc = v cc(on) ? 200 mv, i sink = 10 ma v out(start) ? ? 0.2 v current sense current sense voltage threshold v ilim 0.45 0.5 0.55 v leading edge blanking duration v cs = 2 v, v drv = 90% to 10% t leb 100 195 350 ns overcurrent detection propagation delay dv/dt = 10 v/ s v cs = v ilim to v drv = 10% t cs 40 100 170 ns current sense bias current v cs = 2 v i cs ? 1 ? 1 a
NCL30000 http://onsemi.com 8 typical characteristics figure 3. overvoltage detect threshold vs. junction temperature figure 4. overvoltage hysteresis vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 75 50 25 0 ? 25 ? 50 105 106 107 100 75 25 0 ? 25 ? 50 40 50 60 70 80 v ovp /v ref , overvoltage detect threshold (%) v ovp(hys) , overvoltage hysteresis (mv) 125 figure 5. undervoltage detect threshold vs. junction temperature figure 6. mfp pin internal pull ? down resistor vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0.300 0.305 0.315 0.320 0.325 125 100 75 50 25 0 ? 25 ? 50 0 1 2 6 7 v uvp , undervoltage detect threshold (v) r mfp , feedback pin internal pull ? down resistor (m ) 0.310 figure 7. reference voltage vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 2.46 2.47 2.48 2.49 2.50 2.52 2.53 2.54 v ref , reference voltage (v) 50 125 3 4 5 2.51
NCL30000 http://onsemi.com 9 typical characteristics figure 8. error amplifier sink current vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 6 8 10 12 14 16 i ea(sink) , error amplifier sink current ( a) v mfp = 2.6 v t j , junction temperature ( c) f, frequency (khz) 125 100 75 50 25 0 ? 25 ? 50 85 90 95 105 110 120 125 100 10 1 0.1 0.01 200 0 20 60 100 140 160 t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 25 0 ? 25 ? 50 0.3 0.4 0.5 0.7 0.8 1.0 125 100 75 50 25 0 ? 25 ? 50 264 266 270 274 278 gm, error amplifier transconductance ( s) gm, error amplifier transconductance ( s) ct (offset) , minimum control voltage to generate drive pulses (v) i charge , ct charge current ( a) 1000 50 figure 9. error amplifier source current vs. junction temperature 180 185 190 195 200 205 215 220 ? 50 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) i ea(source) , error amplifier source current ( a) figure 10. error amplifier transconductance vs. junction temperature figure 11. error amplifier transconductance and phase vs. frequency figure 12. minimum control voltage to generate drive pulses vs. junction temperature figure 13. on time capacitor charge current vs. junction temperature v mfp = 0.5 v 210 100 115 40 80 120 180 phase transconductance r control = 100 k c control = 2 pf v mfp = 2.5 vdc, 1 vac v cc = 12 v t a = 25 c 200 0 20 60 100 140 160 40 80 120 180 , phase (degrees) 0.6 0.9 268 272 276
NCL30000 http://onsemi.com 10 typical characteristics figure 14. ct peak voltage vs. junction temperature figure 15. pwm propagation delay vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 75 50 25 0 ? 25 ? 50 4.0 4.5 5.0 5.5 6.0 100 110 120 130 140 150 160 170 figure 16. current sense voltage threshold vs. junction temperature figure 17. leading edge blanking duration vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0.480 0.485 0.490 0.495 0.500 0.505 0.515 0.520 180 190 200 210 220 figure 18. maximum off time in absence of zcd transition vs. junction temperature figure 19. drive resistance vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 165 170 175 180 190 195 200 205 125 100 75 50 25 0 ? 25 ? 50 0 2 4 8 10 14 16 18 v ct(max) , ct peak voltage (v) t pwm , pwm propagation delay (ns) v ilim , current sense voltage threshold (v) t leb , leading edge blanking duration (ns) t start , maximum off time in absence of zcd transition ( s) drive resistance ( ) 125 100 75 50 25 0 ? 25 ? 50 125 0.510 125 100 75 50 25 0 ? 25 ? 50 185 6 12 r oh r ol
NCL30000 http://onsemi.com 11 typical characteristics figure 20. supply voltage thresholds vs. junction temperature figure 21. startup current consumption vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 8 9 10 11 12 13 14 16 18 20 22 24 26 figure 22. switching current consumption vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 2.00 2.02 2.04 2.06 2.08 2.10 2.14 2.16 v cc , supply voltage thresholds (v) i cc(startup) , startup current consumption ( a) i cc2 , switching current consumption (ma) v cc(on) v cc(off) 125 100 75 50 25 0 ? 25 ? 50 2.12
NCL30000 http://onsemi.com 12 theory of operation high power factor requires generally sinusoidal line current and minimal phase displacement between the line current and voltage. normally this is not the case with a traditional isolated flyback topology so the first step to achieve high power factor is to have minimal capacitance before the switching stage to allow a more sinusoidal input current. a simplified block diagram is illustrated in figure 23. since the input bulk capacitor has virtually been eliminated except for a small capacitor, the voltage to the flyback converter now follows a rectified sine shape at twice the line frequency. by employing a critical conduction mode control technique such that the input current is kept to the same shape, high power factor can be achieved. the NCL30000 is a voltage mode, fixed on ? time controller specifically intended for such applications. emi filter ac line input ? cc/cv control NCL30000 controller zero current detect & bias winding primary secondary figure 23. simplified block diagram since the input voltage waveform to the flyback is sinusoidal, with a fixed on ? time control scheme, the current through the transformer primary will increase directly with the line voltage and the average current drawn from the line will have a sinusoidal shape. when the switch is turned off the energy from the primary will be transferred to the secondary. by monitoring the auxiliary winding the controller can detect when the secondary current reaches zero and restart the switching cycle to transfer additional energy to the load. the current in the primary of the transformer starts at zero each switching cycle and is directly proportional to the applied voltage times the on ? time. one of the primary benefits of this crm approach is that we can operate with zero current switching which results in a very efficient architecture for low to medium power applications. a secondary side control loop monitors the average led current and adjusts the on ? time to maintain proper regulation. to achieve high power factor, the control loop bandwidth must be sufficiently low such that the on ? time is constant across a line half cycle. since the off time varies depending on the energy transferred through the transformer and the load, the switching frequency varies with load and line. figure 24 illustrates the theoretical current waveform through the primary and secondary transformer windings. the energy delivered to the load through the transformer will follow the product of voltage and current which is a sine ? squared shape. as a result of this sine ? squared energy transfer, the load will experience ripple at twice the line frequency, either 100 or 120 hz depending on the source. the delivered power through the transformer starts at zero, rises to a peak and returns to zero following the shape of the rectified input line. the 100/120 hz ripple is superimposed on the normal switching waveform of the pwm converter. the maximum on ? time must be set such that the maximum power is delivered at the minimum required operation voltage. the led current required for a particular application is generally specified as an average value. leds can tolerate ripple current as long as the ripple frequency is above the visible range of the human eye and the peak current does not exceed the rating of the leds. just like a standard flyback, the output capacitors filter the pulsing power from the transformer to match the average current required by the led and must be sized appropriately to limit the peak current through the leds.
NCL30000 http://onsemi.com 13 on off mosfet i s (t) i pr(peak) i pr(t) i in(peak) i in (t) figure 24. theoretical switching waveform the led current is compared to a reference and an error signal is passed to the NCL30000 controller to maintain the desired average level. this error signal adjusts the on ? time of the power switch to pass the required energy through the flyback transformer to achieve proper regulation of the led load. just like in a traditional pfc boost converter, the loop bandwidth must be low enough to filter out the twice line frequency ripple otherwise the power factor correction element of the circuit will be compromised. in the event of an open led fault, a constant voltage loop regulates the output voltage across the output capacitor to assure safe operation. the NCL30000 (refer to the block diagram ? figure 1) is composed of 4 key functional blocks along with protection circuitry to ensure reliable operation of the controller. ? on ? time control ? zero current detection control ? mosfet gate driver ? startup and v cc management on time control the on ? time control circuitry (figure 25) consists of a precision current source which charges up an external capacitor (c t ) in a linear ramp. the voltage on c t (after removing an internal offset) is compared to an external control voltage and the output of the comparator is used to turn off the output driver thus terminating the switching cycle. a signal from the driver is fed back to the on ? time control block to dischar ge the c t capacitor thus preparing the circuit for the start of the next switching cycle. the state of v control is determined by the external regulation loop and varies with the rms input voltage and the output load. to achieve high power factor, the regulation loop is designed so that in steady state, the v control value is held constant over a line half cycle. this results in fixed on time operation. the range of on ? time is determined by the charging slope of the c t capacitor and is clamped at 4.93 v nominal. the c t capacitor is sized to ensure that the required on ? time is reached at maximum output power and the minimum input line voltage condition. because the ramp has a wide dynamic range, the control loop can accommodate wide variation of line voltage and load power range.
NCL30000 http://onsemi.com 14 figure 25. on time control comp ct + ? pwm + drv i charge t on v control ? ct (offset) t on(max) v ct v ct(off) v dd drv v control ct (offset) v eah v control off time sequence in a fixed on ? time crm flyback converter, energy stored in the primary of the flyback transformer varies directly with input line voltage on a cycle ? by ? cycle basis. when the switching cycle is terminated, the energy stored in the transformer is transferred to the secondary. the auxiliary winding used to provide bias to the NCL30000 is also used to detect when the current in the secondary winding has dropped to zero. this is illustrated in figure 26. figure 26. ideal crm waveforms with zcd winding drv v cl(neg) v zcd(trig) v zcd(arm) v cl(pos) v zcd(wind),on v zcd(wind),off v zcd(wind) v out i secondary i primary mosfet conduction output rectifier conduction t on t diode t off t sw 0 v 0 v 0 v 0 v 0 a 0 a
NCL30000 http://onsemi.com 15 zcd detection block a dedicated circuit block is necessary to implement the zero current detection . the NCL30000 provides a separate input pin to signal the controller to turn the power switch back on just after the flyback transformer discharges all the stored energy to the secondary winding. when the output winding current reaches zero the winding voltage will reverse. since all windings of the transformer reflect the same voltage characteristic this voltage reversal appears on the primary bias winding. coupling the winding voltage to the zcd input of the NCL30000 allows the controller to start the next switching cycle at the precise time. to avoid inadvertent false triggering, the zcd input has a dual comparator input structure to arm the latch when the zcd detect voltage rises above 1.4 v (nominal) thus setting the latch. when the voltage on zcd falls below 0.7 v (nominal) a zero current event is detected and a signal is asserted which initiates the next switching cycle. this is illustrated in figure 27. the input of the zcd has an internal circuit which clamps the positive and negative voltage excursions on this pin. the current into or out of the zcd pin must be limited to 10 ma with an external resistor. figure 27. zcd operation zcd + ? + demag + ? + reset dominant latch r q s drive zcd clamp r zcd n zcd v zcd(arm) v zcd(trig) q bias winding voltage v trig v arm at startup, there is no energy in the zcd winding and no voltage signal to activate the zcd comparators. to enable the controller to start under these conditions, an internal watchdog timer is provided which initiates a switching cycle in the event that the output drive has been off for more than 180 s (nominal). the timer is deactivated only under an ovp or uvp fault condition which will be discussed in the next section. overcurrent protection (ocp) the dedicated cs pin of the NCL30000 senses the current through the mosfet switch and the primary side of the transformer. this provides an additional level of protection in the event of a fault. if the voltage of the cs pin exceeds v ilim , the internal comparator will detect the event and turn off the mosfet. the peak switch current is calculated using equation 1: i sw(peak) v ilim r sense (eq. 1) to avoid the probability of false switching, the NCL30000 incorporated a built in leading edge blanking circuit (leb) which masks the cs signal for a nominal time of 190 ns. if required, an optional rc filter can be added between r sense and cs to provide additional filtering. this is illustrated below. figure 28. ocp circuitry with optional external rc filter cs + ? + ocp leb drv optional r sense v ilim mfp input the multi ? function pin is connected to the input of the transconductance amplifier, the undervoltage and overvoltage protection comparators. this allows this pin to perform several functions. to place the device in standby, the mfp pin should be pulled below the v uvp threshold. this is illustrated in figure 29. additionally, raising the mfp pin above v ovp will also suspend switching activity but not place the controller in the standby mode. this can be used implement overvoltage monitoring on the bias winding and add an additional layer of fault protection.
NCL30000 http://onsemi.com 16 mfp comp ea + gm uvp + ovp + ovp fault (enable ea) uvp fault c comp v control v ref bias r 1 r 2 r fb + ? + ? + ? v ovp v uvp power good shutdown figure 29. multi ? function pin operation the positive input of the transconductance amplifier is connected to a 2.5 v (nominal) reference. this allows the controller to be used in non ? isolated applications where the mfp could be configured in a more classical feedback input configuration. v cc management the NCL30000 incorporates a supervisory circuitry to manage the startup and shutdown of the circuit. by managing the startup and keeping the initial startup current at less than 35 a, a startup resistor connected between the rectified ac line and v cc charges the v cc capacitor to v cc(on) . turn on of the device occurs when the startup voltage has exceeded 12 v (nominal) when the internal reference and switching logic are enabled. a uvlo comparator with a hysteresis of 2.5 v nominal gives ample time for the device to start switching and allow the bias from the auxiliary winding to supply v cc. example design a practical design case will be used to illustrate the overall power supply functional blocks and the overall design methodology. the power supply specification in this example is listed below and covers an extended universal input range which includes the normal 90 ? 265 vac for global power supplies with an extended upper range to support 277 vac commercial lighting in the united states. ? input voltage: 90 to 305 vac ? power factor: > 0.9 ? output current: 350 ma typical ? led load voltage: 12 to 50 vdc ? full load efficiency: > 83%
NCL30000 http://onsemi.com 17 figure 30. wide input main, 4 ? 15 led 350 ma load schematic 1 l1 + + 4 3 2 1 15v 5.1v t 3 5 NCL30000 mfp comp ct cs zcd gnd drv vcc 1 2 3 5 4 6 7 8 1 1 1 1 1 2 3 4 2 3 4 r2 5k6 c14 100pf c8 10uf q4 mmbta06 t1c c10 4.7 nf r17 100 u4 tl431a u4 tl431a c2 47nf c2 47nf r3 5k6 t1e j1-1 line d13 baw56 c13 100nf r19 10 r19 10 d10 murd330 f1 1 a c5 4700 pf t1d r11 100k spd02n80 q3 c4 100nf c4 r24 47k d11 bzx84c5v6 r31 r31 24k q2 mmbta06 r29 0.2 c9 820 pf r23 1k l2 2.2mh bzx84c56 d12 rt1 r14 4.7k l3 2.2mh j2-2 led cathode u3 lm2904 u3 c12 470uf r10 6.2k r30 24k d4 mra4007 r6 47k r7 47k j2-1 led anode c15 220nf mmbz5245 d9 r26 r26 16k q1 mmbta06 r16 47k j1-2 neutral d8 bzx84c5v1 baw56 d7 r28 470 r28 470 u2 ps2561l_1 c16 100nf c7 1nf c7 27mh r18 100 r18 100 r27 200 r27 200 r20 0.33 q5 mmbta06 q5 mmbta06 r25 1k r25 rv1 v300la4 c1 47nf d5 es1m t1b r22 r22 1k r9 6.2k d6 bas21 r15 100k t1a 3 in1+ in1 ? in2+ in2 ? gnd 8 1 7 out2 out1 vcc 2 5 6 4
NCL30000 http://onsemi.com 18 zero current detection (zcd) the signal controlling the zcd function is taken from the primary bias winding. raising the zcd pin above 1.4 v arms the zero detection circuit. when the pin voltage subsequently falls below 0.7 v, the controller issues the command to turn the power switch back on. the current in or out of the zcd pin must be limited to 10 ma by an external resistor. for this reference circuit a resistance of 47 k provides the required voltage thresholds and limits current to less than 10 ma. feedback control the secondary feedback signal is routed through an optocoupler to the primary side NCL30000 controller. led current is measured with a 0.2 resistor which for 350 ma has a voltage drop of 70 mv. the control loop must be designed to filter out the haversine ripple component to provide an average feedback level to the pulse width controller. in order to maintain high power factor operation, the compensation components around the error amplifier must be set well below 50 / 60 hz. the corner frequency typically falls between 10 and 40 hz. the low frequency response means the control loop will be slow to compensate for rapidly changing situations. in particular, the slow response can introduce overshoot at turn on. to compensate for the slow steady state loop this circuit utilizes a second current control loop to minimize overshoot. the second loop is set for higher than nominal operating current with a very fast response loop. this error amp takes control of the feedback loop until the main error amp is able to respond. in this way the maximum current is limited to safe established level. the current set point of the fast control loop should be set above the peak current of normal operation. u4 is a 2.5 v reference which in conjunction with r26, r27, and r28 establishes the nominal reference voltage of 70 mv mentioned above but also the higher threshold for the fast current loop. in this example, the average output current is 350 ma and the fast loop is set for a 500 ma level. emi filter the emi filter attenuates the switching current drawn by the power converter reducing the high frequency harmonics to within conducted emissions limits. the filter must not degrade the power factor by introducing a phase shift of the current with the line ? to ? line or x capacitors. low total capacitance will minimize this effect. balancing these attributes is a performance tradeoff considering the wide input voltage requirements. a multi ? stage filter consisting of 27 mh common mode inductor and two 2.2 mh differential inductors working with two 47 nf capacitors provides sufficient attenuation to pass conducted emissions requirements. a 4.7 nf ?y1? capacitor bypasses common mode currents created by the power transformer. the low input capacitance approach taken in this design to meet high power factor has the added benefit of not needing inrush current limiting. start ? up circuit and primary bias rapid start up is enhanced by the low current draw of the NCL30000. resistors connected from the rectified ac line to the v cc circuit provide start up power. some of the current is needed for the control chip and bias network while the remaining portion charges up a storage capacitor. when the voltage on the capacitor reaches 12 v nominal, the internal references and logic of the NCL30000 are turned on and the part starts switching. the turn on comparator has hysteresis (2.5 v nominal) to ensure sufficient time for the auxiliary winding to start supplying current directly to the v cc capacitor. resistor divider r9 (6.2 k ) and r15 (100 k ) bias the mfp at the proper voltage to enable the NCL30000. an optional thermal shutdown is implemented with positive temperature coefficient (ptc) thermistor rt1. this thermistor is placed close to the switching fet q3 sensing temperature stress related to load and surrounding temperature. situations causing excessive temperature will cause rt1 to switch to a high impedance turning off the NCL30000. when rt1 cools down, normal operation will resume. transformer design single stage high power factor flyback converters process power in a sine ? squared manner. to support the average led load current, the flyback converter must be capable of processing about 2.5 times the average output power. in this case, the flyback transformer is designed to handle a peak power 43 w to power a 17.5 w led load. the complete details of the transformer design process are found in application note and8451. the NCL30000 is a variable frequency crm controller and as such the transformer determines the operating frequency for a given set of input and output conditions. the transformer turns ratio is controlled by maximum input and output voltage and the ratings of the fet and output rectifier. in this case, the turns ratio from primary to secondary is set at 3.83. power switch on ? time is set at the low line condition of 90 vac or 126 v peak and maximum power of 17.5 w. on ? time will be 15.8 s maximum. primary inductance is calculated from the minimum switching frequency and the conditions listed above as 1.72 mh. peak primary current of 1.15 a is calculated from the primary inductance, applied voltage, and on ? time. core flux density occurs at the peak of the input haversine. primary turns are established from inductance, current, maximum flux density and core geometry as 92 turns. primary turns,
NCL30000 http://onsemi.com 19 current, and maximum flux density set gap size and is approximately 0.014 inches for this transformer. the primary 92 turns divided by the previously calculated ratio of 3.83 establishes secondary turns at 24. #26 triple insulated wire is selected for compliance with safety agency isolation requirements. the primary bias winding must supply 10.2 v to maintain NCL30000 operation. the minimum secondary voltage is 12 v and with 24 turns this means the bias winding needs 20.4 turns. select 22 turns to meet the minimum. for maximum primary to secondary coupling, the primary winding will be split in two equal sections with the secondary winding placed in between. the bias winding is wound on top of the second half of the primary winding. fet switch the NCL30000 controller drives an external power fet controlling the current in the flyback transformer primary. the demonstration board was designed to accept the surface mount dpak or through ? hole to ? 220 power packages. the 15 w target application in 50 c ambient works well with a dpak package. the 800 v 2 a rated spd02n80c3 was chosen. maximum primary current was calculated as 1.15 a. the NCL30000 has a 0.5 v over ? current protection threshold. to allow for 25% margin, a minimum sense resistor of 0.348 is required. a standard 0.33 resistor will be selected. the current sense resistor is placed in the source lead of the power fet and coupled to the controller with a 100 resistor. this resistance in conjunction with the inherent capacitance of the pin filters high frequency noise. in addition, a leading edge blanking (leb) function is included in the controller. this feature avoids spurious activation of the over ? current protection when the power fet is first turned on. on ? time capacitor maximum on ? time is controlled by the c t capacitor. limiting the maximum on ? time reduces component stress in transient situations. the formula below establishes the capacitor value based on charging current of 297 a and maximum voltage threshold of 4.775. the symbol ' represents the effective efficiency of the power transformer stage and secondary losses. it will always be greater than the measured wall plug efficiency which includes losses in the emi filter and primary side compents. (eq. 2) c t 4.94 l pri p out i charge v pk 2 v ct(max) v pk n v out 1 c t 4.94 0.0172 17.5 297 a 0.87 2
90 2 4.775 v 2
90 3.83 50 1 c t 1.1 nf the c t equation is an approximation for simplification. for example, v pk assumes no losses through the diode rectifier bridge and emi filter. this establishes an initial starting point for the c t capacitor and further op timization may be needed. for this design, 0.82 nf was used as the final value. output filter as previously discussed, a high power factor isolated single ? stage converter processes power in a sine squared manner at twice the line frequency. energy storage must be provided on the isolated secondary output just as in normal flyback converters however significantly more storage capacity is required due to the haversine energy transfer characteristic. capacitors are used to store energy as the peak of the 100 or 120 hz haversine delivers maximum power and then releases the stored energy to the load when the haversine falls below the target output power. as the storage capacitor charges and discharges some ripple current is developed in the led load. the magnitude of ripple voltage is controlled by the amount of filter capacitance. in this 350 ma application, two 470 f capacitors are sufficient to provide 30% ripple. high grade electrolytic capacitors should be selected to match driver lifetime with that of the leds. higher temperature rated capacitors enhance lifetime for an optimal solution. to meet ripple requirements in single stage converters filter capacitance is generally high enough that capacitor ripple current is well below device ratings. secondary bias the average mode feedback compensation is intentionally set to a low frequency as described in the feedback section. the relatively large feedback compensation capacitor must charge to normal operating voltage after initial power up which introduces significant delay in regulation. minimizing the required voltage change on the compensation capacitor allows the feedback loop to take control of the output quicker therefore reducing over ? current conditions. maintaining a low bias voltage reduces the required change in compensation capacitor voltage. for this example, a bipolar transistor and 5.6 v zener diode are employed to provide bias voltage of about 5 v. this bias transistor minimizes power loss and allows the led driver to operate over a very wide range of output voltage. this circuit will support as few as 4 leds and up to 15 leds. the secondary bias can be optimized if the application uses a specific number of leds. fewer components and better efficiency can be realized by limiting the output voltage range and adding a secondary bias winding to the transformer. open load protection the led driver behaves like a current source where the output voltage is determined by the forward voltage of the led string. as such, some protection is required to prevent damage in the event of an open led situation. transistor (q5) and zener diode (d12) af fords the necessary protection. a 56 v zener is used in this design example.
NCL30000 http://onsemi.com 20 performance data for 90 to 305 vac led driver shown below in figure 31 is the line regulation and efficiency with a 36.9 v, 12 led load. note the output current does not vary much over the entire input voltage range. the data is based on the use of an efd25 transformer. 300 305 310 315 320 325 330 335 340 345 350 90 115 140 165 190 215 240 265 290 315 input voltage (vac) led current (ma) 77% 78% 79% 80% 81% 82% 83% 84% 85% 86% 87% efficiency (%) led current efficiency figure 31. output current and efficiency with 36.9 v load power factor and total harmonic distortion are shown in figure 32 below. 0 2 4 6 8 10 12 14 16 18 20 90 115 140 165 190 215 240 265 290 315 input voltage (vac) input current thd (%) 0.90 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 power factor (pf) thd pf figure 32. thd and power factor with 36.9 v load
NCL30000 http://onsemi.com 21 load regulation from 12.3 to 52.5 (4 to 15 leds) for 115 and 230 vac input is shown below in figure 4. ef ficiency for this range is also shown. note the tight regulation. efficiency is affected by the startup circuit losses in proportion to load and influenced by higher line voltage. 320 330 340 350 360 370 380 12 17 22 27 32 37 42 47 52 57 led forward voltage (vdc) led current (ma) 74% 76% 78% 80% 82% 84% 86% efficiency 115v led current 230v led current 115v efficiency 230v efficiency figure 33. led current and efficiency at 115 and 230 vac figure 34 shows the current regulation as a function of output voltage (led forward voltage). the control loop has been designed to support 4 ? 15 led based on a forward voltage that ranged from 2.6 ? 3.5 v. the maximum on time of the control loop has been configured to limit the maximum power delivered. this is illustrated at the top of the output voltage ? current transfer function. at the bottom of the curve, even with a short applied to the output, the current is limited to less than 1 a. 0 5 10 15 20 25 30 35 40 45 50 55 60 0 100 200 300 400 500 600 700 800 900 1000 led current (ma) led forward voltage (vdc) figure 34. protection region
NCL30000 http://onsemi.com 22 figure 35 shows output ripple current for 115 vac input and 36.9 (12 led) load operating at 350 ma average. scale factor is 67 ma per division. the low frequency ripple follows the input haversine characteristic of single stage converters. figure 35. output ripple at 115 vac and 36.9 v, 350 ma load figure 36 shows output ripple current at the main switching frequency. scale factor is 33 ma per division. this is the signal superimposed over the haversine ripple component. figure 36. output ripple at 115 vac and 36.9 v, 350 ma load initial start up characteristic is shown in figure 37 below. note the higher current limit controlled by the fast feedback loop and the transition to the main average mode feedback control loop. this shows start up at 115 vac with 36.9 v, 350 ma load. trace 2 is led current at 167 ma per division and trace 3 in applied input voltage at 200 v per division. figure 37. start up characteristic with 36.9 v, 350 ma load typical voltage stress on power fet with 36.9 v, 350 ma load and 305 vac input voltage is shown in figure 38. scale factor is 100 v per division. figure 38. drain to source voltage with 36.9 v, 350 ma load at 305 vac input note that while the power supply was designed to meet agency requirements, it has not been submitted for compliance. standard safety practices should be used when this circuit is energized and in particular when connecting test equipment. during evaluation, input power should be sourced through an isolation transformer. additional application information and tools an evaluation board is available for this 90 ? 305 vac design example. moreover, for applications where it is desired to dim the leds via a triac dimmer, please refer to application note and8448 which explains the steps necessary to configure the NCL30000 for triac dimming. in addition there are two additional triac dimmable reference designs which illustrate a complete design for 90 ? 135 vac or 180 ? 265 vac operation. there is also an microsoft excel spreadsheet tool available to aid in the design process and assist in developing target winding requirements for the transformer.
NCL30000 http://onsemi.com 23 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCL30000/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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